1. Technical Field
The present invention relates to printed wiring boards, and more particularly relates to a wireability enhancement for use on printed wiring boards.
2. Related Art
Printed wiring boards, circuit boards, and cards (hereinafter "PCB's") typically comprise a plurality of "horizontally oriented" layers which include one or more "inner" signal planes (hereinafter "signal planes") that include wiring patterns for delivering signals to various points along a horizontal plane within the PCB, a top plane for receiving components which, like the signal planes, may also include wiring patterns (i.e., the top plane may technically be considered an "outer" signal plane capable of delivering signals to various points on the top plane), and one or more power planes for providing power to various points on the PCB. Connections between and among the signal planes and top plane are made with vertical connections between conductive points or "lands," which reside on the surface of each plane. The vertical connections, referred to as vias, are often implemented as plated through holes (PTH's).
With the advent of more and more complex PCB's, demands have been placed on signal plane designs to provide higher wiring densities or "wireability" in order to service the increasingly complex componentry on the top plane of such PCB's. Accordingly, the wireability of PCB's depends upon the size of the lands, the width of the wire, the space between the wires, the number of signal planes, and the distance between lands. The typical solution for achieving higher density wiring involves either shrinking of the size of the features on the PCB or increasing the number of signal planes. Unfortunately, these solutions generally lead to increased complexity and cost, and almost always adversely affect the PCB's electrical performance.
Assuming additional signal planes cannot be utilized, and it is impractical to further reduce the wire and land size, present designs for signal planes are strictly limited by a fixed channel width. This limitation is described with reference to a simplified example shown in FIGS. 1 and 2. FIG. 1 depicts an example of a top plane 10 of a multi-layered printed circuit board. The top plane 10 comprises a plurality of component lands 12 for receiving componentry, such as pseudo-component 18. As noted, the top plane 10 could also comprise wiring (not shown) between and among the lands 12. The component lands 12, in this case, are spaced in a predetermined pattern. In this case, the pattern is a grid pattern commonly used in the art, such as that implemented with a ball grid array (BGA). Each component land 12 generally comprises a conductive area 14 for receiving a component lead or wire connection, and a via or plated through hole 16 for providing vertical connections to different layers of the PCB. The component lands 12 are generally arranged in a predetermined manner such that each land has a uniform spacing "x" with adjacent lands. Such a predetermined arrangement of lands is preferable because it allows for the easy attachment of components on the PCB. For example, pseudo-component 18 is shown with a plurality of connectors 20 located at predetermined positions that will readily match up with the component lands on the PCB. Consequently, if the arrangement of the circuit lands on the PCB were to be altered, the geometry of the components that are to be attached to the PCB would likewise need to be altered. Such an alteration would clearly be impractical as componentry, which typically comes from many different sources, must adhere to predetermined size specifications. Accordingly, PCB designs are generally required to conform to a particular arrangement with respect to the placement of component lands on the top plane.
In order to deliver a complex network of signals between and among components residing on a top plane of a PCB, an inner signal plane 21 such as that shown in FIG. 2 must be utilized. For each component land 12 on the top plane 10, a corresponding signal land 13 on a signal plane 21 generally exists directly below the corresponding component land 12. A via or PTH may then be used to interconnect the corresponding lands on different planes as required by the particular design. Accordingly, the arrangement of signal lands on the signal plane must generally coincide with the arrangement of component lands on the top plane. Thus, as depicted in FIG. 2, the arrangement of signal lands 13 on the signal plane 21 duplicates the grid depicted on the top plane 10 of FIG. 1. Because wiring on the signal plane 21 must be routed between signal lands 13, the wiring must pass within a channel space 22 having a maximum width of "x." Therefore, as can be seen in FIG. 2, the wiring density 23 on the signal plane 21 is generally limited by a width "x," which directly results from the arrangement of the component lands 12 on the top plane 10.
As noted, given the need for a standard component geometry, the state-of-the-art dictates that the distance between the component lands 12 must be fixed. Accordingly, the wireability on a signal plane 21 has heretofore been limited by the fixed channel width available on the signal plane. Without some method of easily increasing the channel width size in signal plane designs, printed circuit boards will continue to have limited wiring densities.